TMS320F28335PGFA

C2000™ 32-bit MCU with 150 MIPS, FPU, 512 KB flash, EMIF, 12b ADC

Features for the TMS320F28335

· High-performance static CMOS technology

o Up to 150 MHz (6.67-ns cycle time)

o 1.9-V/1.8-V core, 3.3-V I/O design

· High-performance 32-bit CPU (TMS320C28x)

o IEEE 754 single-precision Floating-Point Unit (FPU) (F2833x only)

o 16 × 16 and 32 × 32 MAC operations

o 16 × 16 dual MAC

o Harvard bus architecture

o Fast interrupt response and processing

o Unified memory programming model

o Code-efficient (in C/C++ and Assembly)

· Six-channel DMA controller (for ADC, McBSP, ePWM, XINTF, and SARAM)

· 16-bit or 32-bit External Interface (XINTF)

o More than 2M × 16 address reach

· On-chip memory

o F28335, F28333, F28235: 256K × 16 flash, 34K × 16 SARAM

o F28334, F28234: 128K × 16 flash, 34K × 16 SARAM

o F28332, F28232: 64K × 16 flash, 26K × 16 SARAM

o 1K × 16 OTP ROM

· Boot ROM (8K × 16)

o With software boot modes (through SCI, SPI, CAN, I2C, McBSP, XINTF, and parallel I/O)

o Standard math tables

· Clock and system control

o On-chip oscillator

o Watchdog timer module

· GPIO0 to GPIO63 pins can be connected to one of the eight external core interrupts

· Peripheral Interrupt Expansion (PIE) block that supports all 58 peripheral interrupts

· 128-bit security key/lock

o Protects flash/OTP/RAM blocks

o Prevents firmware reverse-engineering

· Enhanced control peripherals

o Up to 18 PWM outputs

o Up to 6 HRPWM outputs with 150-ps MEP resolution

o Up to 6 event capture inputs

o Up to 2 Quadrature Encoder interfaces

o Up to 8 32-bit timers (6 for eCAPs and 2 for eQEPs)

o Up to 9 16-bit timers (6 for ePWMs and 3 XINTCTRs)

· Three 32-bit CPU timers

· Serial port peripherals

o Up to 2 CAN modules

o Up to 3 SCI (UART) modules

o Up to 2 McBSP modules (configurable as SPI)

o One SPI module

o One Inter-Integrated Circuit (I2C) bus

· 12-bit ADC, 16 channels

o 80-ns conversion rate

o 2 × 8 channel input multiplexer

o Two sample-and-hold

o Single/simultaneous conversions

o Internal or external reference

· Up to 88 individually programmable, multiplexed GPIO pins with input filtering

· JTAG boundary scan support

o IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture

· Advanced debug features

o Analysis and breakpoint functions

o Real-time debug using hardware

· Development support includes

o ANSI C/C++ compiler/assembler/linker

o Code Composer Studio™ IDE

o DSP/BIOS™ and SYS/BIOS

o Digital motor control and digital power software libraries

· Low-power modes and power savings

o IDLE, STANDBY, HALT modes supported

o Disable individual peripheral clocks

· Endianness: Little endian

· Package options:

o Lead-free, green packaging

o 176-ball plastic Ball Grid Array (BGA) [ZJZ]

o 179-ball MicroStar BGA™ [ZHH]

o 179-ball New Fine Pitch Ball Grid Array (nFBGA) [ZAY]

o 176-pin Low-Profile Quad Flatpack (LQFP) [PGF]

o 176-pin Thermally Enhanced Low-Profile Quad Flatpack (HLQFP) [PTP]

· Temperature options:

o A: –40°C to 85°C (PGF, ZHH, ZAY, ZJZ)

o S: –40°C to 125°C (PTP, ZJZ)

o Q: –40°C to 125°C (PTP, ZJZ) (AEC Q100 qualification for automotive applications)